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| CY62167DV18 MoBL(R) 16-Mbit (1M x 16) Static RAM Features * Very high speed: 55 ns * Wide voltage range: 1.65V-1.95V * Ultra low active power -- Typical active current: 1.5 mA @ f = 1 MHz * * * * * -- Typical active current: 15 mA @ f = fmax Ultra low standby power Easy memory expansion with CE1, CE2, and OE features Automatic power down when deselected CMOS for optimum speed and power Available in Pb-free 48-ball VFBGA package consumption by more than 99% when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input and output pins (IO0 through IO15) are placed in a high impedance state when: * Deselected (CE1 HIGH or CE2 LOW) * Outputs are disabled (OE HIGH) * Both Byte High Enable (BHE) and Byte Low Enable (BLE) are disabled (BHE, BLE HIGH) * Write operation is active (CE1 LOW, CE2 HIGH and WE LOW) To write to the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If BLE is LOW, then data from IO pins (IO0 through IO7) is written into the location specified on the address pins (A0 through A19). If BHE is LOW then data from IO pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A19). To read from the device, take Chip Enables (CE1 LOW and CE2 HIGH) and OE LOW while forcing the WE HIGH. If BLE is LOW, then data from the memory location specified by the address pins appear on IO0 to IO7. If BHE is LOW, then data from memory appears on IO8 to IO15. See the "Truth Table" on page 9 for a complete description of read and write modes. Functional Description[1] The CY62167DV18 is a high performance CMOS static RAM organized as 1M words by 16 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery LifeTM (MoBL(R)) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption by 99% when addresses are not toggling. Placing the device into standby mode reduces power Logic Block Diagram DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER 1M x 16 RAM Array SENSE AMPS IO0-IO7 IO8-IO15 COLUMN DECODER BYTE BHE WE OE CE2 CE1 BLE CE2 CE1 Power Down Circuit Note 1. For best practice recommendations, refer to the Cypress application note "System Design Guidelines" at http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05326 Rev. *C A11 A12 A13 A14 A15 A16 A17 A18 A19 BHE BLE * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised April 25, 2007 CY62167DV18 MoBL(R) Product Portfolio Power Dissipation Product Min CY62167DV18LL 1.65 VCC Range (V) Typ[2] 1.8 Max 1.95 55 Speed (ns) Operating ICC (mA) f = 1MHz Typ[2] 1.5 Max 5 f = fmax Typ[2] 15 Max 30 Standby ISB2 (A) Typ[2] 2.5 Max 20 Pin Configuration [3] 48-Ball VFBGA Top View 1 BLE IO8 IO9 VSS VCC IO14 IO15 A18 2 OE BHE IO10 IO11 IO12 IO13 A19 A8 3 A0 A3 A5 A17 DNU A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE1 IO1 IO3 IO4 IO5 WE A11 6 CE2 IO0 IO2 VCC VSS IO6 IO7 DNU A B C D E F G H Notes 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25C. 3. DNU pins must be left floating or tied to VSS to ensure proper operation. Document #: 38-05326 Rev. *C Page 2 of 11 CY62167DV18 MoBL(R) Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage to Ground Potential . -0.2V to VCCmax + 0.2V DC Voltage Applied to Outputs in High-Z State[4, 5] ........................... -0.2V to VCCmax + 0.2V DC Input Voltage[4, 5] ........................-0.2V to VCCmax + 0.2V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (MIL-STD-883, Method 3015) Latch up Current..................................................... > 200 mA Operating Range Range Industrial Ambient Temperature -40C to +85C VCC[6] 1.65V to 1.95V DC Electrical Characteristics (Over the Operating Range) 55 ns Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VCC Operating Supply Current Automatic CE Power down Current - CMOS Inputs GND < VI < VCC GND < VO < VCC, Output Disabled f = fMAX = 1/tRC f = 1 MHz VCC = 1.95V, IOUT = 0 mA, CMOS level IOL = 0.1 mA 1.4 -0.2 -1 -1 15 1.5 2.5 Test Conditions IOH = -0.1 mA Min 1.4 0.2 VCC + 0.2 0.4 +1 +1 30 5 20 A Typ[2] Max Unit V V V V A A mA CE1 > VCC - 0.2V, CE2 < 0.2V, VIN > VCC - 0.2V, VIN < 0.2V, f = fMAX (Address and Data Only), f = 0 (OE, WE, BHE and BLE) CE1 > VCC - 0.2V, CE2 < 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, f = 0, VCC=1.95V ISB2 Automatic CE Power down Current - CMOS Inputs 2.5 20 A Capacitance [7] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = VCC(typ) Max 6 8 Unit pF pF Notes 4. VIL(min) = -2.0V for pulse durations less than 20 ns. 5. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns. 6. Full device AC operation requires linear VCC ramp from 0 to VCC(min) and VCC must be stable at VCC(min) for 500 s. 7. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05326 Rev. *C Page 3 of 11 CY62167DV18 MoBL(R) Thermal Resistance [7] Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board VFBGA 55 16 Unit C/W C/W AC Test Loads and Waveforms VCC OUTPUT 30 pF INCLUDING JIG AND SCOPE R1 VCC R2 GND Rise Time = 1 V/ns Equivalent to: 10% ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns THEVENIN EQUIVALENT RTH OUTPUT V 1.8V 13500 10800 6000 0.80 Unit V Parameters R1 R2 RTH VTH Data Retention Characteristics (Over the Operating Range) Parameter VDR ICCDR tCDR[7] tR[8] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC= 1.0V, CE > V - 0.2V, CE < 0.2V, 1 CC 2 VIN > VCC - 0.2V or VIN < 0.2V 0 tRC Conditions Min 1.0 Typ [2] Max 1.95 10 Unit V A ns ns Data Retention Waveform[9] VCC CE1 or BHE,BLE VCC, min tCDR DATA RETENTION MODE VDR > 1.0V VCC, min tR or CE2 Notes 8. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s. 9. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE. Document #: 38-05326 Rev. *C Page 4 of 11 CY62167DV18 MoBL(R) Switching Characteristics (Over the Operating Range)[10] Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write Cycle tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE [13] Description 55 ns Min 55 55 10 55 25 5 20 [11] Max Unit Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW and CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to LOW Z[11] OE HIGH to High Z [11, 12] ns ns ns ns ns ns ns ns 20 ns ns 55 55 ns ns ns 20 ns ns ns ns ns ns ns ns ns ns 20 ns ns CE1 LOW and CE2 HIGH to Low Z 10 0 CE1 HIGH and CE2 LOW to High Z[11, 12] CE1 LOW and CE2 HIGH to Power up CE1 HIGH and CE2 LOW to Power down BLE/BHE LOW to Data Valid BLE/BHE LOW to Low Z[11] BLE/BHE HIGH to HIGH Write Cycle Time CE1 LOW and CE2 HIGH to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width BLE/BHE LOW to Write End Data Setup to Write End Data Hold from Write End WE LOW to High- [11, 12] WE HIGH to Low-Z [11] 5 Z[11, 12] 55 40 40 0 0 40 45 25 0 10 Notes 10. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in "AC Test Loads and Waveforms" on page 4. 11. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 12. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state. 13. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE, BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write. Document #: 38-05326 Rev. *C Page 5 of 11 CY62167DV18 MoBL(R) Switching Waveforms Read Cycle 1 (Address Transition Controlled)[14, 15] tRC RC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Read Cycle 2 (OE Controlled)[15, 16] ADDRESS tRC CE1 CE2 tACE BHE/BLE tDBE tLZBE OE tDOE DATA VALID tHZOE HIGH IMPEDANCE tHZBE tPD tHZCE DATA OUT tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% 50% ICC ISB Notes 14. The device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. 15. WE is HIGH for read cycle. 16. Address valid before or similar to CE1, BHE, BLE transition LOW and CE2 transition HIGH. Document #: 38-05326 Rev. *C Page 6 of 11 CY62167DV18 MoBL(R) Switching Waveforms (continued) Write Cycle 1 (WE Controlled)[13, 17, 18] tWC ADDRESS tSCE CE1 CE2 tAW WE tSA tPWE tHA BHE/BLE tBW OE tSD DATA IO NOTE 19 tHZOE VALID DATA tHD Write Cycle 2 (CE1 or CE2 Controlled)[13, 17, 18] tWC ADDRESS tSCE CE1 CE2 tSA tAW tPWE tHA WE BHE/BLE tBW OE tSD DATA IO NOTE 19 tHZOE Notes 17. Data IO is high impedance if OE = VIH. 18. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state. 19. During this period, the IOs are in output state. Do not apply input signals. tHD VALID DATA Document #: 38-05326 Rev. *C Page 7 of 11 CY62167DV18 MoBL(R) Switching Waveforms (continued) Write Cycle 3 (WE Controlled, OE LOW)[18] tWC ADDRESS tSCE CE1 CE2 BHE/BLE tAW tSA WE tBW tHA tPWE tSD DATA IO NOTE 19 VALID DATA tHD tHZWE Write Cycle 4 (BHE/BLE Controlled, OE LOW)[18] tWC ADDRESS tLZWE CE1 CE2 tSCE tAW BHE/BLE tSA WE tPWE tSD DATA IO NOTE 19 VALID DATA tHD tBW tHA Document #: 38-05326 Rev. *C Page 8 of 11 CY62167DV18 MoBL(R) Truth Table CE1 H X X L L L L L L L L L CE2 X L X H H H H H H H H H WE X X X H H H L L L H H H OE X X X L L L X X X H H H BHE X X H L H L L H L L H L BLE X X H L L H L L H H L L Inputs/Outputs High Z High Z High Z Data Out (IO0-IO15) High Z (IO8-IO15); Data Out (IO0-IO7) Data Out (IO8-IO15); High Z (IO0-IO7) Data In (IO0-IO15) High Z (IO8-IO15); Data In (IO0-IO7) Data In (IO8-IO15); High Z (IO0-IO7) High Z High Z High Z Mode Deselect/Power Down Deselect/Power Down Deselect/Power Down Read Read Read Write Write Write Output Disabled Output Disabled Output Disabled Power Standby (ISB) Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Ordering Information Speed (ns) 55 Ordering Code CY62167DV18LL-55BVXI Package Diagram Package Type Operating Range Industrial 51-85178 48-ball Fine Pitch BGA (8 x 9.5 x 1 mm) (Pb-free) Document #: 38-05326 Rev. *C Page 9 of 11 CY62167DV18 MoBL(R) Package Diagrams Figure 1. 48-Ball VFBGA (8 x 9.5 x 1 mm), 51-85178 TOP VIEW BOTTOM VIEW O0.05 M C O0.25 M C A B A1 CORNER O0.300.05(48X) 1 2 3 4 5 6 6 5 4 3 2 1 A1 CORNER A B C 9.500.10 9.500.10 0.75 5.25 D E F G H A B C D E 2.625 F G H A B 8.000.10 A 1.875 0.75 3.75 0.55 MAX. 0.25 C B 0.210.05 0.10 C 0.15(4X) 8.000.10 SEATING PLANE 0.26 MAX. C 1.00 MAX 51-85178-** MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05326 Rev. *C Page 10 of 11 (c) Cypress Semiconductor Corporation, 2002-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY62167DV18 MoBL(R) Document History Page Document Title: CY62167DV18 MoBL(R), 16-Mbit (1M x 16) Static RAM Document Number: 38-05326 REV. ** *A *B *C ECN NO. Issue Date 118406 123690 126554 1015643 09/30/02 02/11/03 04/25/03 See ECN Orig. of Change GUG DPM DPM VKN New Data Sheet Changed Advance to Preliminary Added package diagram Minor Change: Changed sunset owner from DPM to HRT Converted from preliminary to final Removed "L" parts Removed 70 ns speed bin Updated footnote #3 Updated Ordering Information table Description of Change Document #: 38-05326 Rev. *C Page 11 of 11 |
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